The present invention relates to methods of fabricating semiconductor structures. More particularly, the present invention relates to methods of fabricating complementary metal oxide semiconductor (CMOS) structures including threshold voltage tuned and scaled gate stacks.
In semiconductor devices including field effect transistors (FETs), threshold voltage of the transistors has been controlled by doping an impurity into the channel region and by appropriately adjusting the dose amount. Threshold voltage control using only this technique, e.g., only through adjustment of the amount of channel impurity, however, raises nonconformities such that an increase in the dose of the impurity to be doped into the channel region may lower ON-state current due to scattering by the impurity, may increase the Gate-Induced Drain Leakage (GIDL) current, and may increase substrate current upon application of substrate voltage. For this reason, low-power-consumption devices having a large amount of impurity doped into the channel region have occasionally resulted in a decrease in the ON-state current, and an increase in the GIDL current.
Another prior art technique that has been used to control the threshold voltage of the FET device is to fabricate a device in which different conductivity type transistors, e.g., nFETs and pFETs, are formed on gate oxides that have a different thickness. That is, it is known to form a device in which the thickness of the gate oxide film of an nFET is different from that of a gate oxide film of a pFET.
In recent years, there has been another trend of using a high dielectric constant film, i.e., a high k dielectric, as the gate insulating film of FET devices. High k dielectrics are those dielectrics that have a dielectric constant that is greater than silicon oxide. Representative high k dielectrics that are useful as a gate insulating material include metal oxides such as, for example, zirconium oxide and hafnium oxide. The use of high k dielectrics as the gate insulating film of a metal oxide semiconductor field effect transistor (MOSFET) can successfully reduce the equivalent silicon oxide thickness in an electrical sense, even if the physical thickness thereof is increased relative to a silicon oxide dielectric film. Hence, high k dielectrics, when used as a gate insulating film, are stable both in a physical sense and in a structural sense. This makes it possible to increase the metal oxide semiconductor (MOS) capacitance for improved MOSFET characteristics, and to reduce gate leakage current as compared with conventional devices in which silicon oxide was used as the gate insulating film.
Although high k dielectrics provide improvements over conventionally used silicon oxide as the gate insulating film in a FET device, the use of the same is not without problems. For example, FET devices including high k gate dielectrics exhibit a non-ideal threshold voltage when the device is used.
In the prior art, various techniques including, for example, forming a threshold voltage adjusting layer interposed between the high k gate dielectric and the gate electrode have been proposed. In such threshold voltage adjusting techniques, the threshold voltage adjusting layers for nFET and pFETs are deposited as blanket layers and need to be patterned by etching for CMOS device fabrication. The acts of deposition and removal of the threshold voltage adjusting layers result in residual traces that impact the threshold voltage of the devices.
Also, in prior art techniques in which a threshold voltage adjusted gate stack is provided that includes a threshold voltage adjusting layer interposed between a high k gate dielectric and a gate electrode, wet etching is typically used in patterning the threshold voltage adjusted gate stacks. When wet etching is employed in patterning the threshold voltage adjusted gate stacks, an undercut of the threshold voltage adjusting layer beneath the gate electrode is observed. The undercutting of the threshold voltage adjusting layer is undesirable since the dimension of the final gate stack would deviate from required criteria. Moreover, the wet etching employed should be benign to the regions being protected, while being potent in the regions needed for removal.